A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

J-A ChengW-S ChangTAI-CHENG LEE2018-09-102018-09-102014-04http://scholars.lib.ntu.edu.tw/handle/123456789/388855[SDGs]SDG7A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidthconference paper10.1109/VLSI-DAT.2014.68348812-s2.0-84903957266