張耀文臺灣大學：電子工程學研究所劉振偉Liu, Chen-WeiChen-WeiLiu2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57234摘要 隨著製程的進步，金屬導線線寬(metal width)變窄而導線長度總和(global wire length)增加，這樣的趨勢造成電源供應導線（power wire）的電阻（resistance）增加。更甚於此，工作電壓（threshold voltage）隨製程縮小產生非線性的變化，造成工作電壓跟電源供應電壓（power supply voltage）的比例以及電源供應網路（Power/Ground network）的電壓降（IR drop）成為非常重要的議題，傳統的電源供應網路分析方法通常需要耗費大量時間來計算，並不適用於平面規劃（floorplan）與電源供應網的共同合成上，為了達成共同合成的目的，我們不僅需要速度夠快且有效的平面規劃演算法（algorithm），也需要有效率且不失精準的電源供應網路分析方法，在這論文中，我們將說明我們的共同合成演算法，這個演算法使用了快速的電源供應網分析法以及B*-tree平面規劃演算法，並且整合在業界的設計流程（design flow）中。我們在實際的晶片以及MCNC benchmark上進行實驗，實驗結果顯示我們的設計方法可以在早期的設計流程中修正電源供應網路的問題，達成一次完成的設計流程。As technology advances, the metal width decreases while the global wire length in- creases. This trend makes the resistance of the power wire increase substantially. Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G network analysis methods are often very computationally expensive, and it is thus not feasi- ble to co-synthesize P/G network with floorplan. To make the co-synthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm, but also a very efficient, yet sufficiently accurate P/G network analysis method. In this thesis, we present a method for floorplan and P/G network co-synthesis based on an efficient P/G network analysis scheme and the B*-tree floorplan representation. We integrate the co-synthesis into a commercial design flow to develop an effective power integrity (IR-drop) driven design methodology. Experimental results based on a real-world circuit design and the MCNC benchmarks show that our design method- ology successfully fixes the IR-drop errors earlier at the floorplanning stage and thus enables the single-pass design convergence.Abstract (Chinese) i Abstract ii List of Tables v List of Figures vi Chapter 1. Introduction 1 1.1 Related Previous Work 2 1.1.1 Dharchoudhury’s Design Flow 3 1.1.2 Yim’s Floorplan-based P/G Network Planning Methodology 4 1.1.3 Haung and Wang’s Floorplan-Based Power Distribution Network Design Methodology 5 1.1.4 Wu and Chang’s Work 5 1.2 Our Contributions 7 1.3 Organization of the Thesis 8 Chapter 2. Problem Formulation 9 2.1 Notations for Describing Power/Ground Network 9 2.2 Power/Ground Integrity Constraints 9 Chapter 3. The Proposed Design Flow 11 Chapter 4. Floorplan and P/G Network Co-synthesis 14 4.1 P/G Mesh Generation 16 4.2 Macro Current Source Modelling 17 4.3 P/G Networks Analysis 18 4.3.1 P/G Network Estimation 20 4.4 P/G Network Co-synthesis Heuristic 22 4.5 Feasible B*-trees with Power Mesh Constraints 23 4.6 The Co-Synthesis Algorithm 27 Chapter 5. Experimental Results 30 5.1 OpenRISC1200 30 5.2 MCNC benchmark 33 Chapter 6. Conclusion and Future Work 36 6.1 Conclusion 36 6.2 Future Work 37 Bibliography 391051117 bytesapplication/pdfen-US電源供應網路平面規劃設計流程電壓降power networkfloorplandesign flowIR-dropthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57234/1/ntu-94-R92943073-1.pdf