A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits

Shanq-Jang RuanRung-Ji ShangFeipei LaiShyh-Jong ChenXian-Jun HuangFEI-PEI LAI2018-09-102018-09-101999-11http://scholars.lib.ntu.edu.tw/handle/123456789/352537A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuitsconference paper10.1109/iccad.1999.8106272-s2.0-0035248598WOS:000167370300013