Lo T.-SWu C.-FChang Y.-HWang W.-C.TEI-WEI KUO2022-04-252022-04-25202115334678https://www.scopus.com/inward/record.uri?eid=2-s2.0-85114365362&doi=10.1109%2fISLPED52811.2021.9502482&partnerID=40&md5=a9add33f9dfcd27d73de8e52dc528267https://scholars.lib.ntu.edu.tw/handle/123456789/607469Aiming to extract the information behind messy data, graph computation is one of the popular big data analysis applications. During running graph computation, large numbers of vertices and edges will be moved between memory and computing units, and these intensive data movements lead to a performance bottleneck. To break the bottleneck, Resistive Random-Access Memory (ReRAM) based crossbar accelerators, which can act as both computing and memory units simultaneously on one chip, are a promising solution to eliminate these data movements. However, running graph computation on crossbar accelerators incurs high power consumption because real-world graphs are too sparse and discrete to unleash the computation capability provided by crossbar accelerators. In contrast to previous works which require extra general-purpose computing units to work with crossbar accelerators, this work proposes a software strategy, called graph-aware crossbar placement strategy, to improve the utilization of crossbar accelerators by clustering graph nodes with strong graph spatial locality. The evaluation results show that the proposed graph-aware crossbar placement strategy can efficiently save the energy consumption of crossbar accelerators. ? 2021 IEEE.AccelerationEnergy utilizationGraph structuresLow power electronicsRRAMEvaluation resultsGeneral-purpose computingHigh power consumptionPerformance bottlenecksPlacement strategyReal-world graphsResistive Random Access Memory (ReRAM)Spatial localityGraph theory[SDGs]SDG7conference paper10.1109/ISLPED52811.2021.95024822-s2.0-85114365362