盧信嘉Lu, Hsin-Chia臺灣大學:電子工程學研究所曾冠澄Tseng, Kuan-ChengKuan-ChengTseng2010-07-142018-07-102010-07-142018-07-102008U0001-2108200816154100http://ntur.lib.ntu.edu.tw//handle/246246/189065本篇論文可以分為兩大部分。第一部份是關於微波多層電路佈局圖中基本形狀的萃取與網路連結圖的生成。此部份應用計算幾何的策略去設計演算法來辨識電路佈局圖中的基本形狀，並將所有的基本形狀連接成一個完整的網路連結圖。第二部份為網路連結圖的後續應用。本論文中的主要應用為檢查各連接埠間直流電是否相通、電容結構的萃取、電容值的估計、電感結構的萃取、電感元件的資訊萃取與自動生成以佈局圖為基礎的電路圖。基本形狀包含矩形與簡單多邊形，可萃取的電路元件包含電容、導線、電感、連通柱、連接埠與接地面。此兩部份為佈局圖對電路圖檢查之前段作業。There are two parts in this thesis. The first part is about the fundamental shape extraction from layout of microwave multi-layer circuit and the generation of net-list diagram. This part applies methodologies of computational geometry to design algorithms to identify the fundamental shapes from layout of circuit, and then connect all fundamental shapes into a complete net-list diagram. The second part is the post-applications of the net-list diagram. The main applications in this thesis are direct current path connectivity check, capacitor structure identification, capacitance estimation, inductor structure identification, inductor segment information extraction, and automatic layout-based schematic generation. The fundamental shapes include rectangles and simple polygons and the extractable circuit components include capacitors, wires, inductors, vias, ports, and ground. These two parts formed the front-end of Layout Versus Schematic (LVS) checking.Chapter 1 Introduction ............ 1 1.1 Background ............ 1 1.1.1 An Example of Microwave Multi-Layer Circuit ............ 1 1.1.2 Introduction of LTCC Technology ............ 3 1.1.3 Introduction of BCB Technology ............ 4 1.2 Purpose ............ 6 1.3 Related Work ............ 7 1.3.1 Layout Extraction ............ 7 1.3.2 Decomposition of Two-Dimensional Simple Polygon ............ 8 1.3.3 DC Path Connectivity Check ............ 11 1.4 Roadmap ............ 12hapter 2 Layout Extraction ............ 15 2.1 Basic Assumptions ............ 15 2.2 Extraction of Rectilinear Shapes ............ 16 2.3 Extraction of Irregular Shapes ............ 21 2.3.1 Extraction of Oblique Corner Wires ............ 21 2.3.2 Extraction of Real Irregular Forms ............ 24 2.4 Summarized Algorithm of Layout Extraction ............ 27 2.5 Uniqueness of Extracted Result ............ 30 2.6 Process of Net-List Generation ............ 30 2.6.1 Decision of Rectangular Connectivity ............ 30 2.6.2 Wire Identification ............ 35 2.6.3 Inclusion of Vias and Other Components ............ 37 2.7 Summarized Flow of Net-List Generation ............ 37 2.8 A Demonstration of Net-List Diagram ............ 38hapter 3 Post-Applications ............ 41 3.1 DC Path Connectivity Check ............ 41 3.2 Capacitor Related Issues ............ 42 3.2.1 Introduction of Capacitor Structures ............ 42 3.2.2 Identification of Capacitor Structures ............ 43 3.2.3 Removal of Redundant Capacitor Structures ............ 43 3.2.4 Capacitance Estimation ............ 45 3.3 Inductor Related Issues ............ 46 3.3.1 Introduction of Inductor Structures ............ 46 3.3.2 Identification of Inductor Structures ............ 48 3.3.3 Extraction of Inductor Segments ............ 57 3.4 Generation of Layout-Based Schematic ............ 60hapter 4 Overall Results ............ 65 4.1 LTCC Circuit Examples ............ 65 4.1.1 2.4 GHz Image-Reject Filter ............ 65 4.1.2 5.25 GHz Bandpass Filter ............ 71 4.1.3 Single Bandpass Filter ............ 76 4.2 BCB Circuit Examples ............ 78 4.2.1 2.4 GHz Lowpass Filter ............ 78hapter 5 Conclusion ............ 83eferences ............ 859564428 bytesapplication/pdfen-US集總元件佈局圖電路圖萃取佈局圖對電路圖檢查電容電感lump elementlayoutschematicextractionLVScapacitorinductorthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189065/1/ntu-97-R95943070-1.pdf