陳信樹臺灣大學：電子工程學研究所洪健凱Hung, Chien-KaiChien-KaiHung2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57378本研究是利用快閃式(Flash)的架構，來實現高速的類比數位轉換器(Analog-to-digital converter)。在此論文中提出一個反向參考電壓仿造前端放大器(Reversed-reference dummy)的方法，成功的修正平均網路的邊界問題，增進前端放大器陣列邊界的線性度。本晶片使用台積電0.18-μm CMOS 製程製作，解析度為六位元，操作時脈頻率為1.6 GS/s，INL為+0.32/-0.28 LSB，DNL為+0.28/-0.28 LSB，在輸入信號頻率為耐奎斯特頻率的情況下，SFDR為44dB，SNDR可達32dB，在1.8伏特的供應電壓下，消耗功率為350mW。A 1.6 GS/s 6-bit CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.56 mm2.Table of Contents IV Table of Figures VI Table of Tables VIII 1 Introduction………………………………………………………………….. 1 2 High-Speed ADC Architectures…………………………………………….. 2 2.1 Folding and interpolating ADC…………………………………………. 3 2.2 Full Flash ADC……………………………………………………......... 6 3 Offset averaging……………………………………………………………… 9 3.1 Offset……………………………………………………………………. 9 3.1.1 Static offset………………………………………………................. 11 3.1.2 Dynamic offset……………………………………………………... 12 3.2 Averaging……………………………………………………………...... 12 3.3 Boundary issue………………………………………………………...... 14 3.3.1 Dummy method………………………………………………......... 14 3.3.2 Termination method………………………………………………... 16 3.3.3 Proposed method…………………………………………………… 17 4 Circuit Implementation……………………………………………………... 22 4.1 Architecture……………………………………………………………... 22 4.2 T/H……………………………………………………………................ 24 4.3 Preamplifier……………………………………………………………... 26 4.4 First stage comparator……………..………………………………......... 28 4.5 Two stages averaging network………………………………………...... 30 4.5.1 Monte Carlo analysis……………………………………………..... 31 4.5.2 Optimization of the averaging network…………………………..... 32 4.6 Second stage comparator & SR latch………………………………........ 35 4.7 Clock generator…………………………………………………………. 37 4.8 Digital Encoder………………………………………………………..... 37 4.9 Simulation result………………………………………………………... 39 5 Performance………………………………………………………………...... 42 5.1 Floor plan and layout considerations…………………………................ 42 5.2 Test setup……………………………………………………………….. 47 5.3 Experiment Result……………………………………………………… 49 5.3.1 The first version of the chip………………………………………... 49 5.3.2 The second version of the chip…………………………………….. 51 6 Conclusion..………………………………………………..………………..... 55 Bibliography………………………………………………………………….. 563515623 bytesapplication/pdfen-US快閃式類比數位轉換器平均flash ADCaveragingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57378/1/ntu-95-R92943106-1.pdf