Huang, P.-C.P.-C.HuangHu, Y.-S.Y.-S.HuTai, H.-Y.H.-Y.TaiHSIN-SHU CHEN2020-06-112020-06-112016https://scholars.lib.ntu.edu.tw/handle/123456789/501236Several hundreds of MS/s to 1GS/s 8-bit low-power ADCs are demanded in various portable applications. Conventional successive-approximation register (SAR) architecture has the benefits of energy efficiency and small area but it suffers from low conversion rate. Recently, multi-bit per cycle SAR [1], multi-comparator SAR [2], pipeline-SAR, and time-interleaved SAR architectures [3] are reported to improve the conversion rate. In this work, an asynchronous two-step single-channel SAR ADC using a charge sharing technique and a self-triggered-latch (STL) technique is proposed to accelerate the conversion rate and reduce the power consumption. This ADC achieves 44.3dB SNDR and 19.1 fJ/c.-s. at 900MS/s with an active core area of 0.0049 mm2 in 40nm CMOS process. © 2016 IEEE.[SDGs]SDG7Reconfigurable hardware; Charge sharing; Conversion rates; Multi-bits; Portable applications; Single channels; Small area; Successive approximation register; Time-interleaved; Energy efficiencyconference paper10.1109/ISCAS.2016.75392012-s2.0-84983438366https://www.scopus.com/inward/record.uri?eid=2-s2.0-84983438366&doi=10.1109%2fISCAS.2016.7539201&partnerID=40&md5=1546c79ea594228cc8909756d645a1b3