胡振國臺灣大學：電子工程學研究所黃思維Huang, Szu-WeiSzu-WeiHuang2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57646以室溫純水陽極氧化技術備製於p型矽上之氧化鋁高介電常數閘極介電層可達到14Å之等效氧化層厚度，所得到之等效介電常數為7.5，並且在相同等效氧化層厚度下具有比二氧化矽低1000倍之閘極漏電流。直流及交直流(直流電壓串聯交流脈波)陽極氧化技術製均被用於金氧半電容器中閘極介電層之成長。在氧化鋁中負偏壓下之電流傳導機制被證實為具有1.6 eV等效位障高度之F-N穿隧。而在正偏壓下之電流出現一飽和之趨勢，代表金屬鋁可被完全氧化而不損及矽基板且無過多二氧化矽之生長。此飽和電流對於由界面陷阱衍生之電容相當敏感並可做為一有效的指標來評估氧化鋁/矽基板間之界面特性。具有最小界面陷阱衍生電容之最佳製程參數控制可經由監測正偏壓下之飽和電流狀況來達成。另外，超薄氧化鋁高介電常數閘極介電層亦以室溫硝酸氧化方式備製於n型4H碳化矽基板之上，在等效氧化層厚度為26Å下可得到9.4之等效介電常數，其閘極漏電流與相同等效氧化層厚度之二氧化矽在同一範圍。經由X光光電子頻譜分析得知氧化鋁/碳化矽界面並無鋁矽酸鹽及碳原子團出現，且金屬鋁可被適當濃度及溫度之硝酸完全氧化而不損及碳化矽基板。其電流傳導機是由金氧半電容器對照光及加溫之響應來研究。在正偏壓下是由具有1.12eV等效位障高度之Schottky發射主控電流傳導，此稍低之位障高度可藉由在氧化鋁/碳化矽界面成長一較薄之二氧化矽來克服。而在負偏壓下之電流傳導機制是由空乏區中之產生-複合電流主控並且受限於少數載子之產生速率。 使用於求取界面陷阱密度之高頻Terman方法被應用在檢測金氧半電容器中等效氧化層電荷之橫向不均勻性。具有不同面積比及平帶電壓之雙並聯電容模型可成功模擬出存在有橫向不均勻等效氧化層電荷之電容-電壓特性曲線，當等效氧化層電荷出現橫向不均勻分佈時，以Terman方法求得之界面陷阱密度被證實會出現負值。此種技術首次被應用於以陽極氧化及硝酸氧化備製之氧化鋁高介電常數閘極介電層，並發現氧化鋁中等效氧化層電荷之橫向均勻性對氧化層製程非常敏感，但可經由選擇適當之氧化與熱退火製程來加以消除。Room-temperature anodic oxidation (anodization) is introduced to prepare ultra-thin aluminum oxide (Al2O3) high-k gate dielectrics on p-Si with equivalent oxide thickness (EOT) down to 14 Å. Both DC and DAC (DC superimposed with AC) anodization techniques were investigated. Effective dielectric constant of k~7.5 and leakage current with 2~3 orders of magnitude lower than SiO2 are observed. The conduction mechanism in Al2O3 under negatively biased region is shown to be Fowler-Nordheim (F-N) tunneling with an effective barrier height of 1.6 eV. It is found that the positively biased current is sensitive to interface trap capacitance (Cit) and can be used as an efficient way to evaluate the Al2O3/Si interfacial property. An optimal process control with minimized Cit via monitoring the positively biased current is demonstrated. Also, ultra-thin Al2O3 gate dielectric on n-type 4H-SiC was prepared by room-temperature nitric acid (HNO3) oxidation. The k~9.4 and EOT of 26 Å are produced, and the interfacial layer and carbon cluster are not observed. The electrical responses of MOS capacitors under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and is limited by the minority carrier generation rate. The high frequency Terman’s method for interface state density (Dit) extraction is applied to inspect the lateral nonuniformity (LNU) of effective oxide charges (Qeff) in MOS capacitors. The two parallel capacitors model is constructed to simulate the LNU charges, and it was shown that negative effective Dit (NED) appears as the LNU occurs in gate oxide. This technique was first used to examine the Qeff distribution in Al2O3 prepared by anodization and HNO3 oxidation. It was found that LNU in Al2O3 is sensitive to oxidation mechanisms and can be eliminated by appropriate oxidation process.Abstract (Chinese)………………………………………………………………………...II Abstract (English)………………………………………………………………………...III Contents…………………………………………………………………………………….IV Figure Captions………………………………………………………………………….VII Table Captions…………………………………………………………………………….XI Chapter 1 Introduction 1-1 Motivation of Research…………………………………………………………….1 1-2 High-k Gate Dielectrics…………………………………………………………….3 1-2-1 Requirements for high-k gate dielectrics………………………………….3 1-2-2 Properties of Al2O3 high-k gate dielectrics………………………………..7 1-3 Equivalent Oxide Thickness Determination of High-k Gate Dielectrics…………..9 1-4 About This Work………………………………………………………………….13 Chapter 2 Al2O3 High-k Gate Dielectrics on p-Si Prepared by Anodization 2-1 Introduction……………………………………………………………………….15 2-2 Anodization of Ultra-Thin Al Film……………………………………………….17 2-3 MOS Capacitors with Al2O3 Gate Dielectrics Prepared by Anodization…............19 2-3-1 Transmission electron microscope results of MOS structure………........19 2-3-2 Capacitance-voltage characteristics……………………………...………20 2-3-3 Current-voltage characteristics in negative bias region………………….22 2-3-4 Current-voltage characteristics in positive bias region…………………..25 2-3-5 Charge trapping behavior…………………………………………….…..27 2-4 Interfacial Properties Between Al2O3 Gate Stacks and Si………………………...29 2-5 Process Control of Anodization…………………………………………………...32 2-6 Summary…………………………………………………………………………..33 Chapter 3 Al2O3 High-k Gate Dielectrics on n-SiC Prepared by HNO3 Oxidation 3-1 Introduction……………………………………………………………………….35 3-2 HNO3 Oxidation of Ultra-Thin Al Film…………………………………………..38 3-3 MOS Capacitors with Al2O3 Gate Dielectrics Prepared by HNO3 Oxidation…….39 3-3-1 Transmission electron microscope results of MOS structure……………39 3-3-2 Chemical bonding analyses of Al2O3 gate stacks and interface………….40 3-3-3 Current-voltage and capacitance-voltage properties…………………….42 3-4 Minority Carrier Responses………………………………………………………45 3-4-1 Minority carrier generation under illumination………………………….45 3-4-2 Intrinsic carrier concentration enhanced by heating……………………..47 3-5 Summary………………………………………………………………………….50 Chapter 4 Lateral Nonuniformities of Effective Oxide Charges in Al2O3 High-k Gate Dielectrics 4-1 Introduction……………………………………………………………………….51 4-2 Experiments……………………………………………………………………….53 4-3 Simulation of LNU Charges……………………………………………………....54 4-4 High Frequency Terman’s Method for Interface Trap Density Extraction………..55 4-4-1 Principles of Terman’s method…………………………………………...55 4-4-2 Origins of negative effective interface trap density……………………...57 4-5 LNU Charges in Al2O3 High-k Gate Dielectrics Prepared by Anodization……….61 4-5-1 Al2O3 high-k gate dielectrics with different effective oxide thickness…...61 4-5-2 Al2O3 high-k gate dielectrics with different annealing temperatures…….64 4-6 LNU Charges in Al2O3 High-k Gate Dielectrics Prepared by HNO3 Oxidation…..65 4-6-1 Al2O3 high-k gate dielectrics on p-Si……………………………………..65 4-6-2 Al2O3 high-k gate dielectrics on n-SiC…………………………………...66 4-7 Summary………………………………………………………………………….68 Chapter 5 Conclusions 5-1 Conslusions……………………………………………………………………….69 5-2 Suggestions for Further Work…………………………………………………….70 Appendix Appendix A SiO2 Prepared by Anodization and Liquid Phase Deposition on SiC…...73 Appendix B Al2O3 High-k Gate Dielectrics on p-Si Prepared by HNO3 Oxidation…...76 Appendix C Theoretical C-V curves with LNU charges for n-type semiconductor…...79 Appendix D Oxidation of thickness-varying strained-Si on SiGe……………………..81 References…………………………………………………………………………………831200932 bytesapplication/pdfen-US氧化鋁陽極氧化硝酸氧化金氧半電容器高介電常數閘極介電層aluminum oxideanodizationnitric acid oxidationMOS capacitorhigh-k gate dielectricsthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57646/1/ntu-94-F90943078-1.pdf