Chien, Y.-H.Y.-H.ChienFu, K.-L.K.-L.FuSHEN-IUAN LIU2020-06-112020-06-11201415497747https://scholars.lib.ntu.edu.tw/handle/123456789/499885https://www.scopus.com/inward/record.uri?eid=2-s2.0-84910095005&doi=10.1109%2fTCSII.2014.2350372&partnerID=40&md5=ae40b4dac0e1b363447d19402b7e404eA 3-25 Gb/s four-channel receiver with noise-canceling transimpedance amplifiers and power-scalable limiting amplifiers is presented. It is fabricated in a 40-nm CMOS process. Each channel provides an overall gain of 64 dB. Ω. The measured input integrated noise is 2.7 μArms, and the measured bit error rate is $< 10-12 for a 25-Gb/s pseudorandom bit sequence of 27-1. The power consumption is 103 mW per channel from a 1.3-V supply. The total area is 1.16 mm2. © 2004-2012 IEEE.Limiting amplifier (LA); noise canceling; power scalable; transimpedance amplifier (TIA)[SDGs]SDG7Operational amplifiers; CMOS processs; Four-channel; Limiting amplifiers; Noise canceling; Power scalable; Pseudo random bit sequences; Bit error ratejournal article10.1109/TCSII.2014.23503722-s2.0-84910095005