指導教授：陳中平臺灣大學：電子工程學研究所李盈翰Lee, Ying-HanYing-HanLee2014-11-302018-07-102014-11-302018-07-102013http://ntur.lib.ntu.edu.tw//handle/246246/263971因為製程的演進，晶片內部的時脈也越來越快，但是晶片與晶片間的傳輸速度卻相對的進步緩慢。因此，設計出一個高速的傳送接收器變成一個重要的課題。 本論文提出了一個高速且低功率耗損應用於晶片間傳輸的電容耦合式接收器，在第一顆晶片裡包含了一個耦合電容(75fF)、一個低擺幅脈衝接收器，以及一個限制放大器。在此種電路架構裡面，信號是以脈衝波形在傳輸線中做傳送，透過電容值的選取，可以有效的控制脈衝波的振幅和長度，以降低ISI，此晶片可運作在12Gb/s速度。脈衝波形經由傳輸線傳遞後再由低擺幅脈衝接收器作訊號回復至NRZ訊號，同時此脈衝接收器也具有低頻補償的功用。在第二顆晶片裡改進了第一顆，使用了線性補償，包含了一個限制放大器、一個低擺幅脈衝接收器、一個線性放大器和一個加法器已達到20Gb/s的操作速度。在第三顆晶片，是做了一個低靜態電流、無輸出電容的低降壓穩壓器，目的是為了能夠提供穩定的電壓源給傳輸晶片系統使用。 第一顆晶片是用TSMC 90nm RF CMOS 製成再做驗證並製作出來，晶片面積為0.135mmX0.056mm。第二顆晶片是用TSMC 90nm UTM CMOS製成再做驗證並製作出來，晶片面積為0.071mmX0.214mm。由模擬結果可以看出第二顆晶片改進了第一顆晶片。 最後，我們也設計了一顆低降壓穩壓器在TSMC 0.35um CMOS製成，做驗證並製作出來，晶片面積為0.477mmx0.742mm。低降壓穩壓器最大負載電流170mA，輸入電壓源(2~6V)皆能穩壓在設定的電壓值，模擬驗證結果在附錄中。Today, the scaling of MOS transistor dimensions is a key factor in the improvement of performance of CMOS technology. High speed links with small AC coupling capacitances are increasing in importance. As a result, the receiver receives a stream of positive and negative pulses corresponding to the rising and falling edges of transmitted data. Receivers which are capable of recovering NRZ signals from these narrow pulses are referred to in this work as AC coupled receivers, and are not to be confused with receivers for links with a relatively large DC blocking capacitor where the received waveforms still look like an NRZ signal with some baseline wander. This thesis introduces a high-speed 12 Gb/s AC coupled receiver architecture for high density interconnects and a modified design for the 1st design which can operate at the 20Gb/s. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from a 75fF capacitor coupled channel. Due to the small coupling capacitances, the transmitted NRZ data at high frequency transitions can be detected at the receiver. The main challenge of the receiver front end is to recover NRZ data from the low swing pulses. In conclusion, 2 chips are designed and fabricated in TSMC 90nm CMOS technology. The 1st proposed chip is using a novel hysteresis circuit path without any compensation technique. The 2nd proposed chip improve the 1st chip integrated with time domain compensation. In addition, we also designed a Low dropout, low quiescent current, output capacitor-less regulator showed in appendix.口試委員會審定書 # 誌謝 II 中文摘要 III ABSTRACT IV Contents VI List OF Figures IX List OF Tables XIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Background of AC Coupled Interconnects 4 2.1 Introduction 4 2.2 Circuit structures of AC Coupled Interconnect 9 2.3 Pulse signaling on ACCI 11 2.4 Frequency response of ACCI 14 2.5 Comparison of ACCI and other I/Os 17 2.6 Summary 19 Chapter 3 1st work ACCI Receiver 20 3.1 Introduction 20 3.2 Hysteresis analysis 22 3.3 Limiting Amplifier 27 3.4 Layout 33 Chapter 4 Measurement Results of ACCI 34 4.1 Measurement setup 34 4.2 Equipments 35 4.3 Layout, results and specification 36 Chapter 5 Modified AC Coupled Design with linear compensation 42 5.1 Introduction 42 5.2 Whole Architecture 42 5.3 Pre amplifier 42 5.4 Hysteretic Analysis 45 5.5 Linear Amplifier 47 5.6 Adder 50 5.7 Layout 52 5.8 Post Layout Simulation 54 Chapter 6 Conclusion and future work 55 Chapter 7 Appendix – LDO Regulator 57 7.1 Introduction Regulators in Power Management 57 7.2 Linear Versus Switching Regulator 59 7.3 Integration 60 7.4 Operational lifetime 61 7.5 Dropout 62 7.6 Block Level 63 7.7 Load Regulation 64 7.8 Line Regulation 65 7.9 Power Supply Rejection 65 7.10 Quiescent Current 66 7.11 Efficiency 66 7.12 Accuracy 67 7.13 Proposed No output Capacitor LDO 68 7.14 Simulation 71 Chapter 8 Measurement Results of LDO 75 8.1 Environment and results 75 8.2 Layout and specification 78 REFERENCE 814180189 bytesapplication/pdf論文使用權限：不同意授權電容耦合接收器晶片與晶片間傳輸低擺幅脈衝接收器互補式傳輸線低降壓穩壓器thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263971/1/ntu-102-R00943038-1.pdf