Chao-Chyun ChenJung-Yu ChangSHEN-IUAN LIU2018-09-102018-09-102007-1215497747http://scholars.lib.ntu.edu.tw/handle/123456789/333726A variable-phase clock buffer that uses a delay-locked loop (DLL) is presented. The variable-phase clock is achieved by switching the multiphase outputs of the divider in the DLL. The output phase is adjustable in a step of π/n where n - 1 (n ≥ 2) is the ratio of two voltage-controlled delay lines in the proposed circuit. The prototype has been fabricated in a 0.18-μ CMOS process to realize the output phases of 0°, 90°, 180°, and 270°. The corresponding measured phase error is 3.24°, 3.46°, 3.89°, and 1.94°, respectively. The measured root-mean-squared jitter is 1.81 ps. The clock buffer consumes 67 mW including I/O circuits from a single 1.8-V supply at 600 MHz. © 2007 IEEE.[SDGs]SDG7Clocks; Clock buffer; CMOS processs; Delay-locked loops; Multiphase-output; Output phase; Root mean squared; Variable phase; Voltage-controlled delay lines; Delay lock loopsjournal article10.1109/TCSII.2007.9061722-s2.0-56349108183WOS:000251944900010