Ho, K.-H.K.-H.HoOu, H.-C.H.-C.OuTsao, H.-F.H.-F.TsaoYAO-WEN CHANG2018-09-102018-09-1020130738100Xhttp://www.scopus.com/inward/record.url?eid=2-s2.0-84879860093&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/380159Capacitance-ratio mismatch in a switched-capacitor circuit could significantly degrade circuit performance. In the nanometer era, the parasitic effects and lengths of interconnects both have significant impacts on the capacitance ratio. This paper presents the first routing work for the problem of coupling-aware length-ratiomatching routing for capacitor arrays in analog integrated circuits. The router adopts a two-stage approach of topology generation followed by detailed routing to route unit capacitors such that the coupling-aware wire length ratio can match the desired capacitance ratio. Given a length ratio, in particular, the length-ratio-matching routing problem can be handled by transforming the problem into an easier classical wirelength minimization one. Experimental results show that our algorithm can solve the addressed problem with substantially smaller costs. Copyright © 2013 ACM.Analog ICs; Physical design; Routing[SDGs]SDG7Analog ICs; Analog integrated circuit; Physical design; Routing; Switched capacitor circuits; Topology generation; Two-stage approaches; Wirelength minimization; Capacitance; Capacitors; Computer aided design; Linear integrated circuits; Problem solvingconference paper10.1145/2463209.24887402-s2.0-84879860093