A bit-level pipelined VLSI architecture for the running order algorithm

Chen, C.-T.C.-T.ChenChen, L.-G.L.-G.ChenHsiao, J.-H.J.-H.HsiaoLIANG-GEE CHEN2018-09-102018-09-101997http://www.scopus.com/inward/record.url?eid=2-s2.0-0031198689&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/329305A bit-level pipelined VLSI architecture for the running order algorithmjournal article10.1109/78.611236