3-Dimensional Vertical Parallel Plate Capacitors in an SOI CMOS Technology for Integrated RF Circuits

Kim, JonghaeJonghaeKimPlouchart, Jean-OlivierJean-OlivierPlouchartZamdmer, NoahNoahZamdmerSherony, MelanieMelanieSheronyLIANG-HUNG LUTan, YueYueTanYoon, MeeyoungMeeyoungYoonJenkins, Keith A.Keith A.JenkinsKumar, MähenderMähenderKumarRay, AsitAsitRayWagner, LawrenceLawrenceWagner2018-09-102018-09-102003-06http://scholars.lib.ntu.edu.tw/handle/123456789/304377https://www.scopus.com/inward/record.uri?eid=2-s2.0-0141761455&partnerID=40&md5=7ab15a85dfde34498a4a1537111bc15aThis paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 urn SOI CMOS technology. An effective capacitance density of 1.76 fF/μm2 is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.CMOS; RF Circuits; SOI; VPPCapacitance; Capacitors; Electric resistance; Q factor measurement; Silicon on insulator technology; Skin effect; Radiofrequency (RF) integrated circuits; CMOS integrated circuits3-Dimensional Vertical Parallel Plate Capacitors in an SOI CMOS Technology for Integrated RF Circuitsconference paper10.1109/vlsic.2003.12211532-s2.0-0141761455