臺灣大學: 電子工程學研究所郭正邦戴承雋Dai, Cheng-JiunCheng-JiunDai2013-04-102018-07-102013-04-102018-07-102011http://ntur.lib.ntu.edu.tw//handle/246246/256822這篇論文敘述實現0.8V基體互補式金氧半動態臨限電壓技術設計低功率系統晶片應用。首先在第一章中先介紹半導體元件以及積體電路在SOC上的低電壓低功率消耗的趨勢。接著在第二章中介紹使用多重臨限電壓和動態臨限電壓技術的基體互補式金氧半動態臨限電壓元件，接下來使用電子設計自動化軟體，讓基體互補式金氧半動態臨限電壓元件設計系統單晶片。第三章藉由16位元的乘法器介紹使用基體互補式金氧半動態臨限電壓元件設計系統單晶片的後段設計中測試和分析，以及相關驗證程序。The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique using MTCMOS and DTMOS technology is presented in chapter 2. Then the approach of chip realization in terms of integration of EDA tools for implementation an SOC chip using the bulk PMOS DTMOS technique is described. In chapter 3, detailed analysis of a test chip a 0.8v 16bit multiplier using the bulk PMOS DTMOS technique via the developed chip implementation technique using integrated EDA tools is described.2994998 bytesapplication/pdfen-US電子設計自動化金氧半動態臨限電壓技術Electronic Design AutomationDTMOSthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256822/1/ntu-100-R98943101-1.pdf