Optimal module set and clock cycle selection for DSP synthesis

Dept. of Electr. Eng., National Taiwan Univ.Chen, Liang-GeeLiang-GeeChenJeng, Lih-GwoLih-GwoJeng2007-04-192018-07-062007-04-192018-07-061991-06http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032225application/pdf371740 bytesapplication/pdfen-USOptimal module set and clock cycle selection for DSP synthesisjournal article10.1109/ISCAS.1991.176734http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032225/1/00176734.pdf