臺灣大學: 電子工程學研究所黃俊郎王麒鈞Wang, Chi-ChunChi-ChunWang2013-04-102018-07-102013-04-102018-07-102011http://ntur.lib.ntu.edu.tw//handle/246246/256794隨著積體電路製程不斷演進，電路時脈的可容忍度變小與不可忽略的製程偏移都使得在速測試（at-speed testing）成為必要的量產測試項目之一。然而，測試時偏高的信號切換率卻成為高品質在速測試的一大挑戰。 在這篇論文，我們提出一個提高在速測試品質的危障消除（hazard elimination）技術。危障影響測試品質的機制如下。首先，危障造成額外的電流消耗、導致不正常的電源網路壓降（power network IR-drop）。這會增加電路的延遲，最後的結果則是良率損失。其次，如果與信號切換的時間重合，危障會造成信號切換提早或延緩到達正反器；其影響的程度遠大於前者所造成者。我們提出的危障消除技術消除對目標路徑延遲影響最大的危障。以s38417電路驗證模擬的結果顯示我們的技術平均可以消除50到80%的危障。As the IC manufacturing technology advances, at-speed testing becomes mandatory due to the shrinking timing budget and non-negligible process variations. However, high-quality at-speed testing is a challenging task due to the excessive circuit switching activity during test application. In this thesis, we proposed a hazard elimination technique to improve at-speed testing quality. Hazards degrade at-speed test quality in the following manners. First, they cause excessive current consumption. The resulting abnormal IR-drop causes extra path delay and leads to yield loss. Second, unexpected hazards can speed up or slow down a signal transition to a much lager extent than IR-drop. The proposed hazard elimination technique effectively removes hazards that exhibit high impact on the target path. Robustly testable paths in s38417 are identified to validate the proposed technique. The average hazard reduction is 50 to 80%.869308 bytesapplication/pdfen-US超大型積體電路測試降低電源壓降危障消除路徑延遲錯誤測試VLSI TestingIR-Drop Effect ReductionHazard EliminationPath Delay Fault TestingRobustly Testable Path Delay Fault Patternthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256794/1/ntu-100-R98943093-1.pdf