Chen, H.-Y.H.-Y.ChenChou, S.-J.S.-J.ChouWang, S.-L.S.-L.WangYAO-WEN CHANG2018-09-102018-09-10200710923152http://www.scopus.com/inward/record.url?eid=2-s2.0-50249165989&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/332272As nanometer technology advances, the post-CMP dielectric thickness variation control becomes crucial for manufacturing closure. To improve CMP quality, dummy feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and lead to explosion of mask data. It is thus desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider wire distribution, the router applies a novel two-pass, top-down planarity-driven routing framework, which employs a new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve more balanced wire distribution than state-of-the-art works. © 2007 IEEE.Design; Masks; Nanotechnology; VLSI circuits; Computer-aided design; Critical area analysis; Delaunay triangulation; Density uniformity; Dielectric thicknesses; Full-chip routing; Grid-based routing; Interconnect performance; Intermediate stage; International conferences; Mask data; Nanometer technologies; Planarity; Planarization; Side effects; Top-down; Voronoi diagrams; Wireconference paper10.1109/ICCAD.2007.43973682-s2.0-50249165989