Dept. of Electr. Eng., National Taiwan Univ.Tang, M.C.M.C.TangSim, J.H.J.H.SimKuoJB2007-04-192018-07-062007-04-192018-07-061993-10https://www.scopus.com/inward/record.uri?eid=2-s2.0-0027805169&doi=10.1109%2f16.249471&partnerID=40&md5=45f4ea0d05bbc02c687707a620b66344This paper reports an analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide. © 1993 IEEEapplication/pdf184409 bytesapplication/pdfen-USComputer simulation; Mathematical models; MOS devices; Semiconductor device models; Semiconductor device structures; Semiconductor doping; Silicon on insulator technology; Voltage measurement; Back gate bias; PISCES analytical model; Silicon germanium channel ultrathin metal oxide semiconductor device; Threshold voltage; Semiconducting silicon compoundsjournal article10.1109/SOI.1993.3445772-s2.0-0027805169http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032372/1/00344577.pdf