顧孟愷臺灣大學：資訊工程學研究所李清新Lee, Ching-HsinChing-HsinLee2007-11-262018-07-052007-11-262018-07-052006http://ntur.lib.ntu.edu.tw//handle/246246/53904Hardware interface design is an elaborative step during intellectual property IP integration. Efficient System-on-a-Chip SoC design depends heavily on IP reuse and high level synthesis. As components of these two methods often have different communication interfaces with bus system, the design of their hardware interface is very time consuming. In this thesis, we propose a hardware interface design architecture which addresses portability, performance and verification. Our hardware interface architecture makes it possible to use data path direct-connection to increase performance. A detection technique is also presented to find out where the bottle neck of the data path is. An experimental result shows that data path direct-connection with bottleneck detection leads to up to 50% improvements in cycle counts. Our architecture also makes it possible to synthesize the hardware interface automatically. An automatic hardware interface synthesis tool is presented.1. INTRODUCTION 11 1.1 Software/hardware co-design methodology 11 1.2 Overview to bus system 14 1.3.1 AMBA bus system 16 1.3.2 AVALON bus system 17 1.3.3 CoreConnect bus system 18 1.3.4 WISHBONE bus system 19 1.3.5 VCI interface protocol 20 1.3 Motivation 21 1.4 Thesis organization 21 2. RELATED WORK 23 2.1 SoC Synthesis with Automatic Hardware Software Interface Generation 23 2.2 Interface Synthesis using Memory Mapping for an FPGA Platform 24 2.3 Bridge over troubled wrappers: automated interface synthesis 25 2.4 Interface design approach for system on chip based on configuration 25 3. AUTOMATIC HARDWARE IP INTERFACE SYNTHESIS 27 3.1 Hardware interface architecture design 27 3.1.1 Bus component logic design 28 3.1.2 Bus connection 29 3.1.3 Data buffering FIFO 30 3.1.4 IP classification 31 3.2 Data buffering FIFO content design 34 3.2.1 FIFO communication ports and signals 34 3.2.2 FIFO synchronization mechanism 36 3.3 Data path direct-connection 37 3.3.1 Feed back information improvement 39 3.4 Automatic hardware interface synthesis tool design 39 3.4.1 Tool execution flow 40 3.4.2 Input and output format of the tool 42 4. CASE STUDY AND EXPERIMENTAL RESULT 50 4.1 Development environments 50 4.2 IP resource 54 4.2.1 IP cores from OPENCORES 54 4.2.2 IP cores from High level synthesis tool: SPARK 56 4.2.3 Custom IP design 58 4.3 Software control interface 59 4.4 IP portability 60 4.5 Case study and experimental result 60 4.5.1 Hardware interface synthesis architecture 60 4.5.2 Data path direct-connection 67 4.5.3 High level synthesis tool result integration 71 5. CONCLUSION AND FUTURE WORK 73 5.1 Conclusion and contribution 73 5.2 Future work 73 REFERENCE 75 APPENDIX A. USER MANUAL 77 APPENDIX B. IP DESCRIPTION FILE EXAMPLES 80974397 bytesapplication/pdfen-US匯流排介面數位矽智財系統單晶片businterfaceDigital IPIPSoCthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53904/1/ntu-95-R93922088-1.pdf