莊晴光臺灣大學：電信工程學研究所陳致嘉Chen, Chih-ChiaChih-ChiaChen2007-11-272018-07-052007-11-272018-07-052007http://ntur.lib.ntu.edu.tw//handle/246246/58976在本論文中，我們提出了一個超高頻帶之可調式無電感CMOS窄頻帶通濾波器。 關於主動式電感的設計和濾波器設計流程的議題也在本文中被討論。此濾波器使用0.18微米CMOS製程製造，量測結果顯示當中心頻率調至436MHz時，頻寬為24MHz的濾波器僅有0.1dB的介入損失、-18dB的返回損失和0.51dB的通帶內漣波。此濾波器晶片面積為333 x 653 μm2，消耗功率為62.5mW，量測的1dB壓縮點為-27.1dBm，雜訊指數為17.6dB。In this thesis, a tunable inductorless CMOS narrow-band bandpass filter at UHF (ultra-high-frequency, 300MHz-3GHz) band is presented. Issues related to active-inductor design and filter design procedure is discussed in detail. The filter is fabricated in 0.18μm CMOS process, measured an insertion loss of 0.1dB, a return loss of 18dB and a 0.51dB in-band ripple with a 436MHz center frequency and 24MHz bandwidth. The filter occupies a chip size of 333 x 653 μm2, with a -27.1dBm input 1dB compression point , a 17.6dB noise figure and a 62.5 mW power consumption.Content 中文摘要 I ABSTRACT II LIST OF FIGURES IV LIST OF TABLE VI CHAPTER 1 INTRODUCTION 1 1.1 Motivation and Literature Survey 1 1.2 Thesis Organization 5 CHAPTER 2 ACTIVE INDUCTOR DESIGN 6 2.1 Principle of Gyrator Inductor 6 2.2 Operational Transconductance Amplifier Design 9 2.2.1 Nauta’s Operational Transconductance Amplifier 9 2.2.2 The Differential Inverter Stage 14 2.2.3 Symmetric Load 15 2.2.4 Current Source Bias Circuit 18 2.2.5 The Proposed Operational Transconductance Amplifier 21 2.3 The Novel CMOS Active Inductor 24 CHAPTER 3 FILTER DESIGN PROCEDURE 26 3.1 Chebyshev LPF Prototype 26 3.2 LPF to BPF Transformation 28 3.3 Admittance Inverters (J-inverters) 30 3.4 Active Filter Design Procedure 32 CHAPTER 4 A UHF BAND TUNABLE INDUCTORLESS CMOS BANDPASS FILTER WITH 26MHZ BANDWIDTH 36 4.1 Circuit Design 36 4.2 Experimental Results 39 4.2.1 S Parameters 39 4.2.2 Linearity 45 4.2.3 Noise Figure 47 4.2.4 Performance Summary and Discussion 48 CHAPTER 5 CONCLUSIONS 50 REFERENCE 51 List of Figures FIG. 1.1 TV TUNER EVOLUTION: (A) CONVENTIONAL TUNER (B) DUAL-CONVERSION TUNER (C) FULLY INTEGRATED TUNER. 4 FIG. 2.1 (A) A TYPICAL GYRATOR INDUCTOR AND (B) THE SMALL SIGNAL ANALYSIS OF A GYRATOR INDUCTOR. 7 FIG. 2.2 THE EQUIVALENT CIRCUIT OF FOUR LUMPED ELEMENT. 8 FIG. 2.3 FREQUENCY RESPONSE DISTORTION DUE TO LIMITED HIGH-Q FREQUENCY RANGE. 9 FIG. 2.4 NAUTA’S BALANCED TRANCSCONDUCTOR. 10 FIG. 2.5 DIFFERENTIAL INVERTER STAGE WITH SYMMETRIC LOADS. 14 FIG. 2.6 SYMMETRIC LOAD. 15 FIG. 2.7 SIMPLIFIED SCHEMATIC OF THE SELF-BIASED REPLICA-FEEDBACK CURRENT SOURCE BIAS CIRCUIT FOR THE DIFFERENTIAL INVERTER STAGE. 18 FIG. 2.8(A) COMPLETE SCHEMATIC OF THE SELF-BIASED REPLICA-FEEDBACK CURRENT SOURCE BIAS CIRCUIT. (B) SCHEMATIC OF THE START-UP CIRCUIT IN (A) 20 FIG. 2.9 SCHEMATIC OF THE NAUTA’S TRANSCONDCTOR EXPRESSED AS SIX INVERTER BLOCK. 22 FIG. 2.10 SIMPLIFIED SCHEMATIC OF THE PROPOSED TRANSCONDCTOR. 22 FIG. 2.11 A SOURCE-COUPLED NMOS DIFFERENTIAL PAIR. 23 FIG. 2.12 (A) THE SIMULATED EQUIVALENT INDUCTANCE VALUE AND (B) Q VALUE OF THE ACTIVE CMOS INDUCTOR. 25 FIG. 3.1 (A) A PROTOTYPE LOWPASS FILTER AND (B) ITS DUAL AND (C) ITS CHEBYSHEV RESPONSE. 28 FIG. 2.2 (A) BANDPASS FILTER CIRCUIT AND (B) ITS FREQUENCY RESPONSE. 30 FIG. 3.3 (A) OPERATION OF A TYPICAL ADMITTANCE INVERTER. (B) IMPLEMENTATION USING CAPACITOR NETWORKS. 31 FIG. 3.4 (A) A GENERALIZED BPF CIRCUIT USING ADMITTANCE INVERTERS. (B) A CAPACITOR-COUPLED PARALLEL LC-RESONATOR FILTER. 32 FIG. 3.5 IMPLEMENTATION OF A SECOND-ORDER CAPACITOR-COUPLED PARALLEL LC-RESONATOR FILTER. 34 FIG. 3.6 THE METHODOLOGY FOR THE DESIGN OF ACTIVE FILTER 35 FIG. 4.1 STRUCTURE OF AN ACCUMULATION-TYPE MOS VARACTOR. 37 FIG. 4.2 CAPACITANCE OF THE ACCUMULATION-TYPE MOS VARACTOR VS. CONTROL VOLTAGE. 37 FIG. 4.3 SCHEMATIC VIEW OF THE FABRICATED BANDPASS FILTER. 38 FIG. 4.4 DIE PHOTO. 38 FIG. 4.5 OFF-CHIP BONDING WIRE TESTS. 40 FIG. 4.6 (A) THE SIMULATED AND MEASURED S11 AND S22 WHILE THE CENTER FREQUENCY IS SET AT THE LOWEST BAND AND (B) THE HIGHEST BAND. 41 FIG. 4.7 (A) THE SIMULATED AND RE-SIMULATED S11 AND S22 WHILE THE CENTER FREQUENCY IS SET 42 FIG. 4.8 SIMULATED FILTER RESPONSE WITH TUNING CHARACTERISTIC. (A) S21 (B) S11 43 FIG. 4.9 MEASURED FILTER RESPONSE WITH TUNING CHARACTERISTIC. (A) S21 (B) S11 43 FIG. 4.10 RE-SIMULATED FILTER RESPONSE WITH TUNING CHARACTERISTIC. (A) S21 (B) S11 44 FIG. 4.11 P1DB AND THD (THIRD HARMONIC DISTORTION) MEASUREMENT SETUP. 46 FIG. 4.12 RAT-RACE BALUN. 46 FIG. 4.13 THE MEASURED PHASE DIFFERENCE BETWEEN THE TWO OUTPUT PORTS OF THE SELF-MADE RAT-RACE BALUN. 46 FIG. 4.14 MEASURED LINEARITY OF THE FILTER (THE CENTER FREQUENCY IS TUNED AT 450MHZ). (A) P1DB (B) SECOND HARMONIC AND THIRD HARMONIC WHILE INPUT POWER IS -10.8DBM 47 FIG. 4.15 NOISE FIGURE MEASUREMENT SETUP. 48 FIG. 4.16 THE SIMULATED AND MEASURED NOISE FIGURE. 48 List of Table TABLE 2.1 OPERATION REGIONS OF THE SYMMETRIC LOAD 16 TABLE 4.1 DIFFERENT BIAS CONDITIONS IN FIG. 4.8-FIG. 4.10. 44 TABLE 4.2 PERFORMANCE SUMMARY. 49766708 bytesapplication/pdfen-US濾波器filterCMOSgyrator inductorthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58976/1/ntu-96-R94942022-1.pdf