臺灣大學: 電子工程學研究所呂良鴻游建威Yu, Chien-WeiChien-WeiYu2013-04-102018-07-102013-04-102018-07-102011http://ntur.lib.ntu.edu.tw//handle/246246/256807近年來隨著市場對通訊的需求越來越高，對高速和高整合密度之有線通訊系統的需求和應用與日俱增。所以本篇論文將介紹以延遲鎖定迴路為基底之時脈產生器的設計與實作。由於有線通訊系統的操作(或參考)頻率會因應用而不同，為了支援更多的應用操作範圍應盡可能加大。然而一般以相位鎖定迴路組成的頻率合成器較難以針對大範圍的參考頻率作出最佳化，甚至會有抖動累積及不穩定的現象。本論文中為了改進以上問題，以延遲鎖定迴路為基底之時脈產生器的架構與應用將被提出。 首先，使用 0.18-μm CMOS 製程的延遲鎖定迴路為基底之時脈與資料回復器架構被提出。透過延遲鎖定迴路產生多相位訊號，進而產生五倍於參考頻率的時脈。而且因為利用提出的半速率相位偵測器，在控制路徑上的速度可以降低，取樣誤差及電路負載可以改善。測試電路架構以及部分電路的設計會提出說明，測量結果也被闡述。 接著，包含抗諧波鎖定的以延遲鎖定迴路為基底之倍頻器被呈現。由於使用了無需重置的相位比較器，在頻率改變時仍然可以正確且快速的鎖定。此外，使用的單端延遲電路及轉態偵測電路可以有效的避免倍頻訊號因訊號週期不同造成的誤差。此電路使用 0.18-μm CMOS 製程實作並且加以量測。With the evolution and scaling down of CMOS technologies, the demand and applications for high-speed and high integration density wire-line communication system has recently grown exponentially. Hence, this thesis illustrates the implementation of the delay-locked loops (DLLs) based clock generator. Because of the operating frequency (or reference frequency) of wire-line communication system depends on the application. The range of operating frequency should be enlarged for more applications. However, the conventional phase-locked loops (PLLs) based frequency synthesizers are hard to optimize for wide reference range, and moreover, the issue of jitter accumulation and stability. Architecture and application about the proposed DLL-based clock generator are presented in order to solve problems that mentioned before. Firstly, a DLL-based clock and data recovery (CDR) architecture implemented with 0.18-μm CMOS process is presented. Using the DLL for generate multi-phase signals. Then, synthesize the signal that multiplies the reference frequency by five. Furthermore, using the proposed half rate phase detector (PD), the speed on controlled-line can be lowered; the error and loading can be improved. The test circuit and building block circuit design are illustrated, and the measurement results are also described. In the second work, a DLL-based frequency multiplier with anti-harmonic locking technique is proposed. With the anti-harmonic PD, when the operating frequency changing the PD can lock correctly in continues time. Moreover, the single-ended delay cell and transition detector can prevent the error by duty cycle distortion. Implemented with standard TSMC 0.18-μm CMOS process, a DLL-based frequency multiplier is proposed and the measurement results are also demonstrated.2130262 bytesapplication/pdfen-US延遲鎖定迴路倍頻器抗諧波鎖定相位偵測器Delay-locked loopFrequency multiplierAnti-harmonic locking phase detectorthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256807/1/ntu-100-R97943016-1.pdf