Wang Y.-PWen C.-CKao C.-CHuang C.-JLiu D.-ZCHIA-HSIANG YANG2021-09-022021-09-022020https://www.scopus.com/inward/record.uri?eid=2-s2.0-85100392984&doi=10.1109%2fGLOBECOM42002.2020.9322225&partnerID=40&md5=5e00f86712a72d650923288ca4f7c47ehttps://scholars.lib.ntu.edu.tw/handle/123456789/580659This paper presents the first 802.11ax compliant iterative detection and decoding (IDD) receiver that supports up to 4 \times 4 1024-QAM MIMO detection in the open literature. Soft-input-soft-output (SISO) MIMO detection is implemented with a lattice reduction aided (LRA) K-best searcher and a max-log list demapper. A hardware-efficient IDD receiver is proposed to achieve the required packet-rate (PER) with a feasible latency. The extrinsic information transfer (EXIT) chart is utilized to reduce the number of iterations for IDD. Given the 802.11ax latency constraint, the performance, power, area (PPA) design space is explored to identify the optimal IDD receiver architecture. 50% of IDD inner iterations are reduced with only a 0.05dB loss in PER. The proposed IDD receiver achieves a 1dB improvement in PER with 3.6\times smaller area and 3.0 \times lower power consumption when compared to the best non-IDD receiver. ? 2020 IEEE.Iterative decoding; MIMO systems; Extrinsic information transfer charts; Iterative detection and decoding; Latency constraints; Lattice-reduction-aided; Lower-power consumption; Number of iterations; Receiver architecture; Soft input soft output; IEEE Standards[SDGs]SDG7conference paper10.1109/GLOBECOM42002.2020.93222252-s2.0-85100392984