Hu V.P.-H.VITA PI-HO HU2021-09-022021-09-022020https://www.scopus.com/inward/record.uri?eid=2-s2.0-85093694855&doi=10.1109%2fVLSI-TSA48913.2020.9203671&partnerID=40&md5=b1a6a7d0e81b4fb88ff6cb903e32009ahttps://scholars.lib.ntu.edu.tw/handle/123456789/581191This paper investigates the impact of gate length scaling on the performance of junctionless (JL) and metal-ferroelectric-metalinsulator- semiconductor (MFMIS) JL transistors. While the performance of JL transistor degrades significantly at gate length of 15 nm due to higher off-current (Ioff), MFMIS JL device can be turned-off with significantly lower Ioff. The performance of MFMIS JL transistor has been compared with inversion mode (IM) device, and result showcases that MFMIS JL transistor exhibits lower Ioff and higher on-to-off current ratio (Ion/Ioff) than MFMIS IM transistor. We analyzed the influence of drain bias and spacer properties on the performance of MFMIS JL and IM devices. Our results show that MFMIS JL transistor with higher Ion/Ioff exhibits better scalability than MFMIS IM transistor for low power applications. ? 2020 IEEE.Ferroelectricity; Field effect transistors; Semiconductor junctions; Gate length; Gate length scaling; Inversion modes; Junctionless transistors; Low power application; Metal-insulator-semiconductors; Off current; Sub-threshold behavior; VLSI circuitsconference paper10.1109/VLSI-TSA48913.2020.92036712-s2.0-85093694855