A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

Graduate Inst. of Electron. Eng., National Taiwan Univ.Wu, Chia-TsunChia-TsunWuWang, WeiWeiWangWey, I-ChynI-ChynWeyWu, An-YeuAn-YeuWu2007-04-192018-07-062007-04-192018-07-062006-05http://ntur.lib.ntu.edu.tw//handle/246246/200704191001111http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001111/1/01693526.pdfapplication/pdf3207336 bytesapplication/pdfen-USA frequency estimation algorithm for ADPLL designs with two-cycle lock-in timeconference paper10.1109/ISCAS.2006.1693526http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001111/1/01693526.pdf