呂學士臺灣大學：電子工程學研究所許彧斌Pin, Hsu YuHsu YuPin2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57602近年來隨著半導體技術的劇烈的發展，因此能利用CMOS技術去結合生物醫學感測器與CMOS電路，進而達成CMOS單晶生醫晶片，實現微小化與低廉價格之生物醫學系統。 其中，類比前端電路功能為信號的處理與調整，是生物醫學系統中的一個重要電路。所以此份論文的目地為，使用TSMC 0.35μm的製程技術完成高性能生物醫學積體電路系統設計，主要的三個電路分別為儀測放大器(IA)、類比前置電路(AFE)與一個自動調變增益之放大器(AGC)。 於本論文之始，提出一個採用截波技術與差微差動放大器架構之儀測放大器，在1.55MH的截波頻率操作下所達到的規格為2.5μV的輸入偏移電壓， 與1nV/√HZ的微小等效輸入雜訊，同時其增益為59dB和頻寬40KHZ。此電路在電壓供應為3V下的功率消耗為641μW。整個晶片的面積是0.96x0.94mm²。 此外，一個高效能之全新生物醫學類比前置電路(AFE)被實現，其特點為僅使用儀測放大器與低通濾波器完成整個系統的設計。本電路的特色為具有58dB-80dB的可程式化增益，31μV的輸入偏移電壓，與70 nV/√HZ的微小等效輸入雜訊，同時實現高的CMRR以及PSRR值，而且整個系統能提供軌對軌的輸入共模範圍、強大的電路趨動能力和軌對軌的輸出信號擺幅。整個晶片的面積是2.44 mm²，此電路在電壓供應為3V下的功率消耗為675μW。 最後，一個典型使用前置回授控制的 CMOS放大器被提出。為了要處理廣大範圍內的放大各種各樣生物醫學信號，本放大器採用前置回授控制的增益控制方式。此外，class-AB的輸出級設計被採用，其目地為增進電路的驅動能力以驅動電路外部的ADC。 最後由量測結果可知，可自動調整的四個增益為0 dB、6 dB、14 dB和20 dB，此時頻寬為55KHZ，而在頻率為500HZ時其等效輸入雜訊為200nV/√HZ，並且達到軌對軌的輸入共模範圍與輸出信號擺幅，以上量測為在輸出端的負載電容為 330 nF時，此電路在電壓供應為3V下的功率消耗為819μW。With the dramatic development of semiconductor technology in recent years, CMOS bio-sensors have been integrated with CMOS circuits, which make realization of CMOS biomedical SoC possible, leading to miniature and low cost biomedical systems. In addition, analog front-end with the function of signal arrangement is a critical component in the biomedical system. In this thesis, an instrumentation amplifier (IA), a new analog front-end (AFE) IC, and an automatic–gain control amplifier (AGC) based on the TSMC 0.35μm technology are proposed to realize high performance biomedical ICs. At first, through the use of chopper technique in the differential difference amplifier, the proposed IA attains a low offset of 2.5μV, a low input referred noise of 1nV/√HZ, a high gain of 59dB with 40KHZ bandwidth under the 1.55MHZ chopping while drawing 641μW from 3-V voltage supply. The die area is 0.96x0.94mm2. Furthermore, a brand new biomedical analog front-end is presented, and meets high performance using only an IA and a LPF. This AFE circuit not only attains high programmable gains of 58dB-80dB, a low offset of 31μV, a low input referred noise of 70 nV/√HZ, and high CMRR as well as PSRR but also provides rail-to-rail input common-mode range, high driving ability, and rail-to-rail output signal swing. The die area is 2.44 mm2 and the power consumption is 675μW from 3-V voltage supply. Finally, a novel CMOS feed-forward automatic-gain control (FFAGC) amplifier is presented. The proposed amplifier is intended to amplify various kinds of biomedical signals with a wide dynamic range characteristic. The feed-forward automatic-gain control (FFAGC) technique is adopted to provide appropriate gain settings. Furthermore, a class-AB output stage realizes large driving ability for an external ADC. The experimental results showed that variable gains of 0 dB, 6 dB, 14 dB, and 20 dB with a bandwidth of 55 kHz, input referred noise of 200nV/√HZ at 500 Hz, rail-to-rail input common-mode range, and rail-to-rail output dynamic range can be achieved while the output loading capacitor is 330 nF. The power consumption is 819 μW with 3 V of supply voltage.Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 The fundamentals of analog front-end 5 2.1 Introduction 5 2.2 Offset and noise in CMOS circuit 6 2.1.1 Basic CMOS amplifier 6 2.1.2 Noise spectrum analysis 7 2.1.1 Noise bandwidth 8 2.3 Low noise and low offset circuit techniques 9 2.3.1 Classification 9 2.3.2 Autozero technique 10 2.3.3 Chopper technique 11 2.3.3.1 Basic principle 11 2.3.3.2 Chopper modulation 12 2.3.3.3 Effect of chopping on the noise of chopper amplifier 13 2.3.3.4 Residual offset 15 2.3.3.5 Chopping frequency select 17 2.4 Circuit analysis of analog front-end 17 2.4.1 Noise analysis of noninverting and inverting amplifiers 17 2.4.1.1 Introduction 17 2.4.1.2 Noise analysis of noninverting amplifier 18 2.4.1.2 Noise analysis of inverting amplifier 19 2.4.2 Instrumentation amplifier 21 2.4.2.1 Traditional instrumentation amplifier 21 2.4.2.2 Proposed instrumentation amplifier 23 2.4.2.3 Residual Offset Reduction of DDA with Chopper Technique 23 2.4.3 Low-pass filter 25 2.4.4 Automatic-gain control 27 2.5 Summary 29 Chapter 3 Instrumentation amplifier 31 3.1 Introduction 31 3.2 Circuit architecture of differential difference amplifier incorporating chopper technique 32 3.3 Circuit description of differential difference amplifier incorporating chopper technique 34 3.3.1 Overview 34 3.3.2 The nested-Miller frequency compensation 35 3.3.3 Low noise design 38 3.3.4 Chopper modulator 40 3.3.5 Clock generator 41 3.4 Simulation results 42 3.5 Measurement result 48 3.5.1 Measurement setup 48 3.5.1.1 Die photograph and PCB design 48 3.5.1.2 AC Response measurement Setup 49 3.5.1.3 Noise measurement Setup 50 3.5.1.4 Experimental Results 51 3.5.2 Experimental Results 52 3.6 Summary 56 Chapter 4 A Biomedical Analog Front-End 59 4.1 Introduction 59 4.2 The architecture of proposed analog front-end 60 4.3 Design and implementation of proposed biomedical analog front-end 61 4.3.1 Instrumentation amplifier and digital controller 61 4.3.2 Rail-to-rail differential difference amplifier 62 4.3.2.1 Overview of the circuit 62 4.3.2.2 Rail-to-rail differential difference input stage 63 4.3.2.3 Constant transconductance (gm) circuit 67 4.3.2.4 Transimpedance amplifier with class-AB output stage 68 4.3.2.5 Low noise design 71 4.3.3 Three-Order Bessel Low-Pass Filter 73 4.3.4 On-chip oscillator 76 4.4 Simulation results 77 4.4.1 Instrumentation amplifier 77 4.4.2 Three-order Bessel low-pass filter 82 4.4.3 On- chip oscillator 83 4.4.4 Analog front-end simulation 83 4.5 Measurement setup and experimental results 88 4.5.1 Die photograph and PCB design 88 4.5.2 Experimental Results 90 4.5.2.1 Instrumentation amplifier 90 4.5.2.2 Three-order Bessel low-pass filter 94 4.5.2.3 Analog front-end 97 4.6 Summary 99 Chapter 5 A Feed-Forward Automatic-Gain Control Amplifier for Biomedical Applications 101 5.1 Introduction 101 5.2 System architecture and specifications 102 5.3 The proposed circuit 104 5.3.1 Digitally controlled VGA 104 5.3.2 Rail-to-rail operational amplifier 105 5.3.3 Peak detector circuit 106 5.3.4 Level decode and gain decode logic 107 5.4 Simulation results 108 5.4.1 Simulated rail-to-rail op and VGA 108 5.4.2 Simulated FFAGC 111 5.5 Measurement setup and experimental results 115 5.5.1 Measurement setup 115 5.5.1.1 Die photograph and PCB design 115 5.5.1.2 AGC measurement setup 116 5.5.2 Experimental results 116 5.6 Summary 119 Chapter 6 Conclusion 121 Reference 1274988871 bytesapplication/pdfen-US截波差微差動放大器類比前置電路放大器chopperdifferential difference amplifieranalog front endamplifierthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57602/1/ntu-96-R94943123-1.pdf