Tai-Yu KuoYen-Ting LinChun-Nien ChenHUEI WANG2019-10-242019-10-242019https://www.scopus.com/inward/record.uri?eid=2-s2.0-85069950075&doi=10.1109%2fmwsym.2019.8700795&partnerID=40&md5=fa321f8c9da9eff542607f365f04f2edA 65-nm CMOS transmitter composed of a high linearity I/Q up-converter and a class-A power amplifier is presented for the 5G application. To achieve high linearity, the splitting cascode topology at the transconductance (gm) stage of the up-converter is adopted. A power amplifier is cascaded to the high linearity I/Q up-converter to amplify both fundamental and intermodulation signals. The measurement results of the transmitter demonstrate a conversion gain of 18.5 dB and an output 1-dB compression point (OP1dB) of 13.5 dBm with only 22-mW dc consumption of the up-converter and 134.4 mW of the power amplifier. The two-tone measurement results exhibit two sweet-spots of third-order intermodulation (IM3). The transmitter achieves 32 dBm output third-order intercept point (OIP3) by an improvement of 9 dB. The output power of the transmitter with the third-order intermodulation distortion (IMD3) under -30 dBc is 8.6 dBm. © 2019 IEEE.5G mobile communication.; CMOS technology; intermodulation distortion; millimeter wave circuits; mixers; power amplifiers10.1109/mwsym.2019.87007952-s2.0-85069950075