C.-H. WengC.-C. LinY.-C. ChangTSUNG-HSIEN LIN2018-09-102018-09-102011-1215497747http://scholars.lib.ntu.edu.tw/handle/123456789/366791https://www.scopus.com/inward/record.uri?eid=2-s2.0-83655198349&doi=10.1109%2fTCSII.2011.2172709&partnerID=40&md5=872c9b617a0af5412bc6e23606124cd7A second-order continuous-time delta-sigma modulator incorporating a proposed 4-bit asynchronous sequential quantizer and a digital excess-loop-delay (ELD) compensation technique is presented. The sequential operation of the proposed quantizer facilitates low power consumption while the hardware-efficient digital compensation technique allows the modulator to accommodate ELD. With a 1-MHz bandwidth and a 60-MHz sampling rate, the measured peak signal-to-noise-and-distortion ratio and dynamic range are 62 and 67 dB, respectively. Fabricated in a 90-nm CMOS, this chip consumes only 0.89 mW from a 1.2-V supply. © 2006 IEEE.Asynchronous circuits; Delta-sigma modulator; Digitally assisted design; Excess loop delay (ELD)Continuous time systems; Delay circuits; Delta sigma modulation; Energy efficiency; Signal to noise ratio; Asynchronous circuits; Compensation techniques; Delta sigma modulator; Digital compensation; Excess loop delays (ELD); Low-power consumption; Sequential operations; Signal to noise and distortion ratio; Modulatorsjournal article10.1109/TCSII.2011.21727092-s2.0-83655198349?WOS:000296234100014