Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique

B. ChungJ. B. KuoJAMES-B KUO2018-09-102018-09-102006-09http://scholars.lib.ntu.edu.tw/handle/123456789/325388Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Techniqueconference paper