Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications

R. ChenR. LiuJ. B. KuoJAMES-B KUO2018-09-102018-09-102008-10http://scholars.lib.ntu.edu.tw/handle/123456789/342564This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology, has a 24.6% reduction in total power consumption.[SDGs]SDG7Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applicationsconference paper10.1109/icsict.2008.47349972-s2.0-60649118187