Kuo Y.-TLin W.-CChen CHsieh C.-HLi J.C.-MJia-Wei Fang EHsueh S.S.-Y.CHIEN-MO LI2022-04-252022-04-25202110893539https://www.scopus.com/inward/record.uri?eid=2-s2.0-85123054369&doi=10.1109%2fITC50571.2021.00012&partnerID=40&md5=3e6dffb9d18703e5973fd632343dd15bhttps://scholars.lib.ntu.edu.tw/handle/123456789/607011We propose a new methodology to predict minimum operating voltage (Vmin) for production chips. In addition, we propose two new key features to improve the prediction accuracy. Our proposed accumulative learning can reduce the impact of lot-to-lot variations. Experimental results on two 7nm industry designs (about 1.2M chips from 142 lots) show that we can achieve above 95% good prediction. Our methodology can save 75% test time compared with traditional testing. To implement this method, we will need to have a separate test flow for the initial training and accumulative training. ? 2021 IEEE.Chip Performance PredictionMachine LearningProcess variationMachine learningChip performanceChip performance predictionKey featureMachine-learningMinimum operating voltages (Vmin)Operating voltagePerformance predictionProcess VariationProduction testVoltage predictionForecastingMinimum Operating Voltage Prediction in Production Test Using Accumulative Learningconference paper10.1109/ITC50571.2021.000122-s2.0-85123054369