Huang TWu S.-SKlopp JYu P.-HLIANG-GEE CHEN2022-04-252022-04-25202102714310https://www.scopus.com/inward/record.uri?eid=2-s2.0-85109024208&doi=10.1109%2fISCAS51556.2021.9401565&partnerID=40&md5=d533cd62a649d3003f5f563ea342de70https://scholars.lib.ntu.edu.tw/handle/123456789/607246CNN-based stereo matching methods achieve great performance but come with high computational requirements. Pruning a CNN can reduce the complexity but may in turn lead to memory conflicts, lowering throughput. Our proposed architecture and memory mapping technique aim at reducing conflicts to exploit extremely sparse stereo matching networks. To maintain a high utilization of processing elements, we decompose the de-convolution operation into several convolution operations. The proposed architecture provides a 2.1× speed up over SCNN. Compared to the software implementation, only 0.01% performance drop is observed, so that the proposed architecture obtains state-of-the-art accuracy compared to existing sparsity aware hardware implementations. ? 2021 IEEEDeconvolutionMemory mappingPE utilizationSparsity-aware CNNVLSI architectureConvolutionMemory architectureComputational requirementsEfficient architectureHardware implementationsHigh utilizationsProcessing elementsProposed architecturesSoftware implementationStereo matching methodNetwork architecture[SDGs]SDG3[SDGs]SDG16conference paper10.1109/ISCAS51556.2021.94015652-s2.0-85109024208