Dept. of Electr. Eng., National Taiwan Univ.K-J HsiaoTAI-CHENG LEE2018-09-102018-09-102005-06http://scholars.lib.ntu.edu.tw/handle/123456789/318024A delay-locked loop (DLL)-based frequency multiplier is designed for the ultrawideband (UWB) Mode-1 system. This clock generator with 528-MHz input reference frequency can achieve less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. The UWB clock generator has been fabricated in a 0.18-)-μm CMOS process and consumes only 54 mW from a 1.8-V supply while exhibiting a sideband magnitude of -35.3 dB and -94 dBc/Hz phase noise at the frequency offset of 50 kHz.application/pdf666687 bytesapplication/pdfDelay-locked loops; Frequency multiplier; UWBCMOS integrated circuits; Delay circuits; Frequency synthesizers; Spurious signal noise; Delay locked loops; Frequency multipliers; Sideband magnitude; UWB; Broadband networksconference paper10.1109/VLSIC.2005.14693292-s2.0-33644655407