Cheng, C.-C.C.-C.ChengTsai, Y.-M.Y.-M.TsaiChen, L.-G.L.-G.ChenChrakasan, A.P.A.P.rakasanLIANG-GEE CHEN2018-09-102018-09-102010http://www.scopus.com/inward/record.url?eid=2-s2.0-78649832503&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/3557973GPP LTE requires a 100 Mbps of peak bandwidth, and the instantaneous throughput demand changes with different applications. Fixed sub-block parallel turbo decoding scheme introduces bit-error rate (BER) performance drop when the block length is short. In this paper, an LTE turbo decoder implemented on a 0.66 mm2 die in a 65 nm CMOS technology is presented. An adaptive sub-block parallel (ASP) decoding scheme that improves the BER performance by up to 2.7 dB while maintaining the same parallelism is developed. A DVFS engine combining with an early-termination scheme is also developed. It generates the supply voltage and the clock rate that lead to the lowest energy consumption given the output bandwidth requirement. The measured energy consumption is 0.077∼0.168 nJ per bit per iteration and 0.39∼0.85 nJ per bit. © 2010 IEEE.[SDGs]SDG7100 Mbps; 3gpp lte; 65nm CMOS technology; Bandwidth requirement; BER performance; Block lengths; Clock rate; Decoding scheme; Demand changes; Energy consumption; Parallel scheme; Sub-blocks; Supply voltages; Turbo decoders; Turbo decoding; Bit error rate; CMOS integrated circuits; Energy utilization; Integrated circuit manufacture; Integrated circuits; Mobile telecommunication systems; Decodingconference paper10.1109/CICC.2010.5617396