A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation

Lin S.-CJAMES-B KUOHuang K.-TSun S.-W.2023-06-092023-06-092000189383https://www.scopus.com/inward/record.uri?eid=2-s2.0-0033884611&doi=10.1109%2f16.830986&partnerID=40&md5=b6d3b17b7a27c1384b74af7947e890cbhttps://scholars.lib.ntu.edu.tw/handle/123456789/632457This paper reports an analytical inverse narrow-channel effect threshold voltage model for shallow-trench-isolated (STI) CMOS devices using a conformai mapping technique to simplify the two-dimensional (2-D) analysis. As verified by the experimentally measured data and the 2-D simulation results, the analytical model predicts well the inverse narrow-channel effect threshold voltage behavior of the STI CMOS devices. Based on the study, the inverse narrow-channel effect also affects the saturation-region output conductance of a small-geometry STI CMOS device in addition to the short-channel effect. © 2000 IEEE.Conformai mapping technique; Inverse narrow-channel effect; Small geometry; STI[SDGs]SDG14Computational geometry; Computer simulation; Conformal mapping; Gates (transistor); Semiconductor device models; Threshold voltage; VLSI circuits; Deep submicron devices; Inverse narrow channel effect; Shallow trench isolation (STI); CMOS integrated circuitsA closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolationjournal article10.1109/16.8309862-s2.0-0033884611