A broadband chip-level power-bus model feasible for power integrity chip-package co-design in high-speed memory circuits

H.-H. ChuangC.-J. HsuJ. HongC.-H. YuA. ChengJ. KuTZONG-LIN WU2018-09-102018-09-102010-02http://scholars.lib.ntu.edu.tw/handle/123456789/359401[SDGs]SDG7A broadband chip-level power-bus model feasible for power integrity chip-package co-design in high-speed memory circuitsjournal article10.1109/TEMC.2009.20356142-s2.0-77249150378WOS:000274730800027