The reduction of keep-out zone (?10×) by the optimized novel trench structures near the through silicon vias for the application in 3-dimensional integrated circuits

Liao, M.H.M.H.LiaoMING-HAN LIAO2020-01-132020-01-132013https://scholars.lib.ntu.edu.tw/handle/123456789/447962The reduction of keep-out zone (?10×) by the optimized novel trench structures near the through silicon vias for the application in 3-dimensional integrated circuitsjournal article10.1063/1.48261962-s2.0-84886522459https://www.scopus.com/inward/record.uri?eid=2-s2.0-84886522459&doi=10.1063%2f1.4826196&partnerID=40&md5=7ff2572cf0b932fbeb711488d41617d6