Huang, Zheng-YuZheng-YuHuangPEI YUN TSAI2024-09-182024-09-182010https://www.scopus.com/record/display.uri?eid=2-s2.0-77956002139&origin=resultslisthttps://scholars.lib.ntu.edu.tw/handle/123456789/721442Paris, 30 May 2010 through 2 June 2010In this paper, we aim to design and implement a high-throughput QR decomposition architecture for 4 x 4 MIMO signal detection problems. A real-value decomposed MIMO system model is handled and thus the channel matrix to be processed is extended to the size 8x8. Instead of direct factorization, we propose a QR decomposition scheme by cascading one complex-value and one real-value Givens rotation blocks, which can save 44% hardware complexity. The systolic array is adopted for hardware implementation to facilitate pipeline design. Then, the requirement of skewed inputs to the conventional complex-value QR-decomposition systolic array is improved and 37% of delay elements are removed. The real-value Givens rotation stage is implemented by a stacked triangular systolic array to match with the throughput of the complex-value one. We have implemented the proposed design in 0.18 μm CMOS technology with 152K gates. From post-layout simulations, the maximum operating frequency can achieve 90.09MHz. The proposed scheme not only reduces the hardware complexity, but also supports high throughput for MIMO-OFDM signal detection up to 2.16 Gbps under stationary channels. ©2010 IEEE.conference paper10.1109/ISCAS.2010.55373582-s2.0-77956002139