Lin, J.-M.J.-M.LinYi, H.-E.H.-E.YiYAO-WEN CHANG2018-09-102018-09-10200213502409http://www.scopus.com/inward/record.url?eid=2-s2.0-0036698653&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/298316The module placement problem is to determine the co-ordinates of logic modules in a chip such that no two modules overlap and some cost (e.g. silicon area, interconnection length, etc.) is optimised. To shorten connections between inputs and outputs and/or make related modules adjacent, it is desired to place some modules along the specific boundaries of a chip. To deal with such boundary constraints, we explore the feasibility conditions of a B*-tree with boundary constraints and develop a simulated annealing-based algorithm using B*-trees. Unlike most previous work, the proposed algorithm guarantees a feasible B*-tree with boundary constraints for each perturbation. Experimental results show that the algorithm can obtain a smaller silicon area than the most recent work based on sequence pairs.Algorithms; Boundary conditions; Constraint theory; Logic design; Perturbation techniques; Simulated annealing; Trees (mathematics); B-trees; Boundary constraint; Logic modules; Module placement; Simulated annealing algorithm; Multichip modulesjournal article10.1049/ip-cds:200204332-s2.0-0036698653WOS:000178389700008