Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate

J. B. KuoC. H. HsuC. P. YangJAMES-B KUO2018-09-102018-09-102004-10http://scholars.lib.ntu.edu.tw/handle/123456789/310517Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gateconference paper10.1109/edssc.2005.16352902-s2.0-43549123719