國立臺灣大學電子工程學研究所張耀文2006-07-262018-07-102006-07-262018-07-102004-07-31http://ntur.lib.ntu.edu.tw//handle/246246/20007http://ntur.lib.ntu.edu.tw/bitstream/246246/20007/1/922215E002016.pdf在深次微米設計中，當操作頻率到達數千赫茲 時，晶片上面的電感效應已經不能再被忽略。因 此，如何去精確地萃取出來傳輸連線結構的阻抗跟 電感值變得十分重要。大部份以前的阻抗跟電感萃 取著重在矩形切割的研究上，但是隨著時代的進 步，有許多非一般性結構的晶片，例如X-結構與 Y-結構連線結構已經被發表出來或是可以提供製 造。很明顯一般的矩形切割方式對於這些特殊的連 線結構已經不敷使用，所以在這個計畫中，我們提 出了一個用三角形切割方式配合面積分方法來處 理阻抗萃取問題，最後我們會跟這方面有名的軟體 來做驗証，証明我們方法的正確性以及較多的彈 性。As the operation frequency reaches gigahertz in very deepsubmicron designs, the effect of on-chip inductance on circuit performance can no longer be neglected. Therefore, it is desired to extract transmission-line impedance and inductance accurately. Most of the previous works on impedance and inductance extraction are based on rectangular discretization which has been shown effective for the classical Manhattan based IC interconnect structures. As technology advances, however, more general IC interconnect structures, such as the X-based and Ybased interconnect structures, have been introduced or even already in production. Those general interconnect structures allow wires to be routed with non-Manhattan shapes. For the non-Manhattan interconnect structures, rectangular discretization is obviously not sufficient. In this project, we propose to use the surface integral formulation with triangular discretization to extract impedance and inductance for the general IC transmission-line structures. Comparative studies with the famous FASTHENRY, FASTIMP, and IE3D show that our approach is flexible and effective.application/pdf278766 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所inductancesurface integralextractiongeneral interconnect structures電感面積分萃取一般連線結構reporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/20007/1/922215E002016.pdf