Dept. of Electr. Eng., National Taiwan Univ.Chen, Chun-ChiehChun-ChiehChenTsao, Hen-WaiHen-WaiTsao2007-04-192018-07-062007-04-192018-07-061996-02N/Ahttps://www.scopus.com/inward/record.uri?eid=2-s2.0-0030084449&doi=10.1049%2fel%3a19960234&partnerID=40&md5=77e936ddee9291ba72b2d30bebf469d0A 5V, 100MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous Letter (1995), the proposed SHA is implemented by an open-loop structure using the 'gain-enhanced unity-gain amplifier' to avoid the stability problem and achieve higher operation speed. Simulation results which agree well with experimental results have been obtained to demonstrate the accuracy of the proposed circuit.application/pdf292349 bytesapplication/pdfen-USAmplifiers; CMOS integrated circuits; Sample and hold circuitsAmplifiers (electronic); Aspect ratio; Computer simulation; Electric waveforms; Mathematical techniques; Multiplying circuits; Signal theory; Signal to noise ratio; Transconductance; Bias voltage; Closed loop structure; Data acquisition system; Differential mode gain; Gain enhancing factor; Microphotograph; Sample and hold circuits; CMOS integrated circuitsjournal article10.1049/el:199602342-s2.0-0030084449http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910042581/1/00490922.pdf