0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications

W. J. H. LinC. Y. ChienJ. B. KuoJAMES-B KUO2018-09-102018-09-102009-01http://scholars.lib.ntu.edu.tw/handle/123456789/3519550.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applicationsconference paper