Liang, Jun-WeiJun-WeiLiangJiang, Iris Hui-RuIris Hui-RuJiangChiu, Kai-HsiangKai-HsiangChiuSu, Tung-YuTung-YuSu2026-01-122026-01-122025-12-0421563357https://www.scopus.com/record/display.uri?eid=2-s2.0-105024126113&origin=resultslisthttps://scholars.lib.ntu.edu.tw/handle/123456789/735227With the advancement of high-speed and energy-efficient optical interconnect and computation, photonic integrated circuits (PICs) have become a promising alternative to traditional CMOS circuits. A PIC can be synthesized by mapping the binary decision diagram (BDD) of target functions to optical switches and combiners. However, excessive signal attenuation along the light propagation may require extra optical-electrical signal conversion, thus introducing unwanted delays. In this paper, we aim to overcome this deficiency during logic synthesis: First, we optimize the signal efficiency factor by applying the concept of harmonic mean to optimize DC combiners. Second, we properly arrange these proposed techniques in an optimal sequence of operations to form our main framework. Furthermore, we propose partial harmonic mean to minimize the hardware cost under an efficiency factor constraint. Experimental results show that our framework outperforms the state of the art in terms of efficiency factor.falseefficiency factorharmonic meaninteger partitionlogic synthesisPhotonic integrated circuit[SDGs]SDG7journal article10.1109/jetcas.2025.36402232-s2.0-105024126113