An Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Design

Yeh, Yi-JongYi-JongYehKuo, Sy-YenSy-YenKuo2009-02-272018-07-062009-02-272018-07-062002http://ntur.lib.ntu.edu.tw//handle/246246/141994application/pdf194202 bytesapplication/pdfen-USAn Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Designjournal articlehttp://ntur.lib.ntu.edu.tw/bitstream/246246/141994/1/09.pdf