國立臺灣大學電子工程學研究所Chiueh, Tzi-DarTzi-DarChiuehYang, Jin-BinJin-BinYangWu, Jen-ShiJen-ShiWu2006-11-152018-07-102006-11-152018-07-102001-10http://ntur.lib.ntu.edu.tw//handle/246246/200611150121858http://ntur.lib.ntu.edu.tw/bitstream/246246/200611150121858/1/9306.pdfA new frequency synthesizer based on combining the analog phase-locked loop (PLL) and the all digital PLL (ADPLL) is presented. The frequency synthesizer achieves high frequency resolution, broad frequency range, high switching speed, and low supply voltage. The oscillator is controlled by both the digital control word and the control voltage of the analog PLL. It is an array oscillator implemented by symmetric load differential inverting buffers which provide better rejection to supply noise and fabrication variance. Fractional- divider and delay interpolation technique are employed to enhance the divider resolution without inducing jitter. A binary search algorithm is used to find the proper digital frequency control word, which can be saved for later use and greatly speed up the frequency switching process. Fabricated using a 0.6- m SPTM CMOS process, the synthesizer achieves a frequency range of 54–154 MHz with a frequency error less than 1 ppm and a frequency switching time less than 10 s. The chip consumes very little power and draws 47 mW from a 2-V supply voltage.application/pdf225498 bytesapplication/pdfzh-TWFrequency synthesizermixed-signal controlphase-locked loop (PLL)[SDGs]SDG7journal article10.1109/82.974785http://ntur.lib.ntu.edu.tw/bitstream/246246/200611150121858/1/9306.pdf