2022-02-012024-05-17https://scholars.lib.ntu.edu.tw/handle/123456789/693850摘要： 研究次世代的半導體材料在奈米技術掌握的情況下有了突破性的發展，許多具有獨特特性的新材料被發現，被視為能取代現有以矽為主體的半導體製程的明日之星。其中以石墨稀為主體的所開發的新型電子元件已經被成功的應用到各個領域，包含奈米電晶體、綠能電子、可彎式電子、量子光學以及醫療領域的應用。雖然石墨稀擁有卓越的電子、機械、光學等特性，並且也是現有二維材料中唯一擁有全晶圓單晶沉積技術制備成員，要能結合到大型積體電路的設計，只有具有半導體性質的石墨稀奈米帶可以。 然而在開發能取代傳統矽為下一代半導體材料石墨稀奈米帶技術仍有許多問題需要解決，包含(1) 如何製作全晶圓尺寸的石墨稀奈米帶，並將製成均一化；(2) 如何降低奈米帶的寬度不均問題，使得每一個奈米待電晶體的電子特性相同；(3) 如何能將全晶圓的石墨稀奈米帶製作成單一方向；(4) 修補石墨稀奈米代的邊界因為製程而產生缺陷；(5) 現有單晶技術只能在鍺基板上面，如何拓展到其他半導體基版；(6)將單晶奈米帶技術應用到其他新穎二維材料；(7) 降低生產成本，提高良率 。 本計劃為了解決長久以來研發能取代新半導體材料所遇到的主要困境 – 新穎材料無法大規模均一化生產，以石墨稀奈米帶為切入點，探討如何將生產單晶二維材料奈米帶均一化的製程，提出了以下面五種方向的同步研究，以提供半導體產業鏈 大規模晶圓尺寸的石墨稀奈米帶的技術為目的: &#8226;研究非等向性石墨稀奈米帶的生長技術，研究石墨稀奈米帶的生長條件與基底生長靶材晶相的關係 &#8226;透過奈米分子自主排列的先期研究成果，研發在大尺寸石墨稀奈米帶均勻切割的技術 &#8226;探討在可生長單晶石墨稀基底材料上面，修復石墨稀邊界缺陷的生長技術 &#8226;高良率轉置石墨稀奈米帶在生長單晶石墨稀基底材料到可製作半導體元件基底的方法 &#8226;拓展單晶生長技術到其他新穎二維材料<br> Abstract: We propose a universal fabrication procedure for FinFETs based on 2D materialsnanoribbons that featuring low cost, wafer-scale capable, atomic-level defectless, and compatible to the state-of-art techniques. The designated process includes 5 steps: (1) a wafer-scale 2D materials depositions, (2) pre-patterned with traditional lithography techniques, (3) nano-patterning through the Directed-Self-Assembly (DSA) and etching, (4) post defect repairing through equilibrium growth condition and (5) Transistors fabrication. In general, single crystal 2D material is pre-deposited on the whole surface of the handling wafer and patterned into hundreds of nanometers ribbon structures through traditional lithography/etching process. A further nanostructure patterns are enabled by registering the small molecular block polymers on the periodic ribbons’ surfaces to form the regulated sub10nm features. After transferring the template to the bottom 2D materials, the edge defects can be further repaired through controlling the growth/etching equilibrium conditions of the 2D material deposited process. At the same time, with slightly control the source gas combination, the width of the 2D material nanoribbon can be gradually reduced to the lowered number. Different from the traditional Top-Down approaches in the Si FinFETs process, this procedure combines the mature material growth techniques, integrates the skills in molecular dynamics and self-assembly, and merge the traditional Top-Down production schematics to achieve the low cost and wafer-scale applications with edge repairing process. With introduction the DSA and material growth skills, lithography cost and the defect problems at nano scale dimensions can be resolved, and wafer-scale 2D materials nanoribbon transistors can be prepared in aligned, with controlled width and repaired edge conditions. Through this approach, high performance 2D materials transistors can be well-prepared.石墨稀奈米帶全晶圓修復生長規則排列Graphene nanoribbonwafer-scalealignedCVDEdge-Repair