李泰成臺灣大學:電機工程學研究所陳科璁Chen, Ke-TsungKe-TsungChen2010-07-012018-07-062010-07-012018-07-062009U0001-0502200920040100http://ntur.lib.ntu.edu.tw//handle/246246/188029　　隨著3G時代的來臨，從短距離到動輒數百公里的無線電資料與語音傳輸技術不斷地進展，使得無線行動通訊在人類生活中扮演相當重要的角色。由於高輸入動態範圍、高傳輸速率與低功率的需求，使得設計類比數位轉換器（ADCs）也必須達到較高解析度、頻寬與低功率的規格方能滿足這些嚴苛條件外，也可寬鬆無線接收器類比前端（analog front-end）電路部份的設計要求。　本論文在系統層面設計上，著重於電路延遲效應補償的介紹以及時脈抖動的研究；在電路層面設計上，透過仔細地分析、推導與模擬，針對元件非理想效應來取捨評估元件規格。論文主要應用於寬頻分碼多工擷取（WCDMA）無線電通訊上，電路實現在訊號頻寬5-MHz，操作在320-MHz取樣頻率（即過取樣率為32）上之一位元量化三階低通連續時間型三角積分類比數位資料轉換調變器（delta-sigma A/D modulator）。量測結果達56-dB動態範圍（dynamic range）與最大SNR值51.3-dB（相當於8.2-bit有效位元）。利用2P4M 3.3-V台積電CMOS 0.35-μm製程與R-C積分器技術，電流功率消耗13.6-mA。　　With the advent of the third-generation (3G) era, wireless technologies on data and sounds transmission ranging from short distances to even hundreds of kilometers at its constant advances have had mobile telecommunications to be a quite important role in human life. Due to the demand for high input dynamic range, data rate, and low power, designing analog-to-digital (A/D) data converters must achieve not only the stringent conditions of higher resolution, higher bandwidth, and low power consumption, but also relax the requirements for the analog front-end parts of radio receivers.　This thesis on system-level design focuses on introduction to the compensation of circuit-delayed effects and research to clock jitter; on circuit-level design it shows a better trade-off estimate on specifications through carefully analyzing, deriving out, and simulating the nonideal effects of circuit elements. The proposed implementation of the single-bit third-order low-pass continuous-time delta-sigma analog-to-digital (A/D) modulator can be mainly applied for wideband-code-division-multiple-access (i.e., so-called WCDMA) radio communications with 5-MHz signal bandwidth at sampling frequency of 320-MHz. Experimental results show that a signal-to-noise ratio (SNR) of 51.3dB (i.e., 8.2-bit ENOB) and a dynamic range of 56dB in the 2P4M 3.3-V TSMC CMOS 0.35-μm process with a R-C integrator topology. The measured current consumption is 13.6-mA.誌　　謝　....................................................................................................................... I文摘要　.................................................................................................................... III文摘要　..................................................................................................................... V　目錄　..................................................................................................................... X　目錄　................................................................................................................. XIV一章 緒論 ................................................................................................................ 1.1 研究動機 .............................................................................................. 1.2 論文貢獻 .............................................................................................. 3.3 論文組織 .............................................................................................. 3二章　Sigma-Delta（ΣΔ）三角積分調變器概論 ................................................... 5.1 性能衡量標準 ...................................................................................... 5.1.1 SNR / SNDR / SFDR ............................................................ 5.1.2 動態範圍（Dynamic Range）................................................. 6.1.3 量化雜訊（Quantization Noise）............................................ 7.1.4 過取樣率（Oversampling Ratio）........................................... 9.1.5 雜訊移頻（Noise-Shaping）.................................................. 10.2 ΣΔ ADC系統 ...................................................................................... 11.3 ΣΔ調變器的基本架構 ....................................................................... 13.3.1 一階ΣΔ調變器 .................................................................... 13.3.2 二階ΣΔ調變器 .................................................................... 15.3.3 高階ΣΔ調變器 .................................................................... 16.3.4 CIFB架構 ............................................................................. 17.3.5 CIFB與CIFF架構比較 ....................................................... 18.3.6 MASH架構 .......................................................................... 20.4 ΣΔ調變器的零點分佈最佳化 ........................................................... 22.5 ΣΔ調變器的穩定法則 ....................................................................... 24三章 ΣΔ調變器之迴路濾波器設計 ..................................................................... 25.1 傳統離散時間（DT）型ΣΔ調變器之迴路濾波器設計方法 ......... 25.2 連續時間（CT）型ΣΔ調變器之迴路濾波器設計方法 ................. 27.3 介紹Sliding Mode理論設計CT ΣΔ調變器 ................................... 31.4 DT與CT ΣΔ調變器的優缺點比較 ................................................ 34四章　系統層面設計與元件非理想性 .................................................................. 37.1 系統層面設計 .................................................................................... 37.2 運算放大器（OPAmp）的非理想效應 ........................................... 44.2.1 有限的OPAmp增益頻寬積對調變器的影響 ................... 44.2.2 有限的OPAmp迴轉率對調變器的影響 ........................... 47.2.3 有限的OPAmp增益對調變器的影響 ............................... 48.3 時脈抖動 ................................................................................. 49.3.1 時脈抖動對於DT ΣΔ調變器的影響 ................................ 50.3.2 時脈抖動對於CT ΣΔ調變器的影響 ................................ 51.4 迴路濾波器係數變異的影響 ............................................................ 53五章　電路設計與實現 .......................................................................................... 56.1 以理想電路元件實現的架構 ............................................................ 56.2 實際電路元件的設計 ........................................................................ 61.2.1 偏壓電路 .............................................................................. 62.2.2 運算放大器 .......................................................................... 64.2.3 類比數位轉換器DACs ........................................................ 66.2.4 比較器（一位元量化器）.................................................... 67.2.5 D-Latch與時脈產生器 ........................................................ 71.3 整體電路模擬的結果 ........................................................................ 72六章 電路佈局與晶片測試 .................................................................................. 74.1 電路佈局與模擬 ................................................................................ 74.2 量測環境與結果 ................................................................................ 81.2.1 測試板設計 .......................................................................... 82.2.2 測試環境裝備 ....................................................................... 82.2.3 量測結果 ............................................................................... 84.2.4 相關文獻比較 ....................................................................... 86七章 結論與未來展望 .......................................................................................... 88.1 結論 .................................................................................................... 88.2 未來展望 ............................................................................................ 88考文獻 ...................................................................................................................... 903316179 bytesapplication/pdfen-US類比數位轉換連續時間單位元量化寬頻分碼多工擷取電流控制超取樣三角積分調變器Analog-to-digital conversioncontinuous-timesingle-bit quantizationWCDMAcurrent-steeringoversamplingdelta-sigma modulatorthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/188029/1/ntu-98-J94921044-1.pdf