電機資訊學院: 電子工程學研究所指導教授: 郭正邦胡勝凱Hu, Sheng-KaiSheng-KaiHu2017-03-062018-07-102017-03-062018-07-102015http://ntur.lib.ntu.edu.tw//handle/246246/276475本篇論文探討了部分解離絕緣體上矽N型金氧半元件模型考慮浮動基體效應效應與汲極導致能障降低效應之次臨界區間的分析。第一章先簡介絕緣體上矽金氧半元件之特性，並且比較部分解離絕緣體上矽和完全解離絕緣體上矽之間的差異。第二章說明了部分解離絕緣體上矽N型金氧半元件電流傳導機制與等效模型，以及分析使用不同通道長度元件對次臨界區間的影響。第三章則探討加入了正背閘極及使用不同的載子生命期時對次臨界區間的影響。第四章則是結論。The thesis reports subthreshold analysis of PD SOI NMOS device considering floating body effect and drain-induecd barrier lowering. Chapter 1 gives a brief introduction about SOI CMOS devices and the scaling trends, including the comparison of the difference between the PD SOI and the FD SOI CMOS devices. Chapter 2 describes current conduction mechanism and equivalent circuit of the PD SOI NMOS device. The subthreshold analysis of the PD SOI NMOS device considering the various channel lengths has been performed. Chapter 3 discusses the PD SOI NMOS device in subthreshold region considering the back gate bias effect and various different carrier lifetimes. Chapter 4 is conclusion.2557290 bytesapplication/pdf論文公開時間: 2025/8/17論文使用權限: 同意有償授權(權利金給回饋學校)部分解離絕緣體上矽次臨界斜率PDSOIsubthreshold-S-factorthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/276475/1/ntu-104-R99943102-1.pdf