Dept. of Electr. Eng., National Taiwan Univ.Lian, Chung-JrChung-JrLianLIANG-GEE CHENChang, Hao-ChiehHao-ChiehChangChang, Yung-ChiYung-ChiChang2007-04-192018-07-062007-04-192018-07-062001-02http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021264https://www.scopus.com/inward/record.uri?eid=2-s2.0-33646909277&doi=10.1109%2fASPDAC.2001.913273&partnerID=40&md5=90a1d14e97f70faf93867d1f8fb04227A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-μm single-poly triple-metal process. It can run up to 40 MHz at 3.3 V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc. © 2001 IEEE.application/pdf311506 bytesapplication/pdfen-USDelay; Digital cameras; Discrete cosine transforms; Hardware; Image coding; Image storage; Quantization; Read-write memory; System-on-a-chip; Testing[SDGs]SDG9Application specific integrated circuits; Computer aided design; Computer hardware; Cosine transforms; Digital cameras; Discrete cosine transforms; Image coding; Integrated circuit design; Optical image storage; Reconfigurable architectures; System-on-chip; Testing; Chip implementation; Delay; Design and implementations; Fully pipelined architecture; Quantization; Quantization tables; Run-time reconfigurable; System on a chip; Digital image storageconference paper10.1145/370155.37024610.1109/ASPDAC.2001.9132732-s2.0-33646909277http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021264/1/00913273.pdf